1. Field of the Invention
The present invention is in the field of integrated circuits. More particularly, the present invention relates to an integrated circuit of the type which is formed of multiple fine-dimension circuit elements disposed in a planar central area on a die or chip of semiconductor material. Around the central area of the chip, and around the multitude of fine-dimension circuit elements thereon, is disposed a peripheral array of electrical contact pads by which the integrated circuit is electrically connected to a package structure for the integrated circuit chip, and to external electrical circuitry. The present invention relates to such an integrated circuit having a conductive ground plane overlying the active fine-dimension circuit elements, and carried upon an electrically insulative passivation layer of the integrated circuit. The conductive ground plane is connected electrically to the ground-potential electrical contact pads of the integrated circuit.